1. Field of the Invention
This invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a memory device.
2. Description of the Related Art
With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with high efficiency and low cost are produced based on different objectives. The dynamic random access memory (DRAM) is such an important semiconductor device in the information and electronics industry. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells.
Most DRAMs have one transistor and one capacitor in one DRAM cell. The memory capacity of the DRAM has reached 512 megabits (or further more than 1024 megabits). Therefore, under increasing integration it is required to shrink the size of the memory cell and the transistor so as to manufacture the DRAM with high memory capacity and high processing speed. A 3-D capacitor structure can itself reduce occupied area in the semiconductor substrate, so the 3-D capacitor, such as a deep trench capacitor, is applied to the fabrication of the DRAM of 1024 megabits and above.
FIGS. 1A-1D show a conventional method for forming gate lines or metal lines of a semiconductor device. Referring to FIG. 1A, a substrate 100 comprising an array region 102 and a periphery region 104 is provided, and a gate layer 106 is formed on top of both the array region 102 and the periphery region 104. Next, a silicon nitride layer 108 is formed on the gate layer 106. A polysilicon hard mask layer 110 is formed on the silicon nitride layer 108. A photoresist layer 112 is formed on the polysilicon hard mask layer 110.
Referring to FIG. 1B, the photoresist layer 112 is defined by lithography process to form a plurality of photoresist patterns 112a, wherein parts of the photoresist patterns 112a in the array region 102 are more concentrated than those in the periphery region 104. Next, the polysilicon hard mask layer 110 is etched using the photoresist patterns 112a as a mask, forming a plurality of openings 114. Thereafter, referring to FIG. 1C, the photoresist patterns 112a are removed, and the silicon nitride layer 108 is etched using the etched polysilicon hard mask layer 110 as a mask to pattern the silicon nitride layer 108 according to the pattern of the etched polysilicon hard mask layer 110. Referring to FIG. 1D, the polysilicon hard mask layer 110 is removed. The gate layer 106 is then etched using the etched silicon nitride layer 108 as a mask to pattern the gate layer 106 according to the pattern of the etched silicon nitride layer 108.
In the above conventional method, when etching the polysilicon hard mask layer 110 or other layers using the photoresist patterns 112a as a mask, non-conventional line widths and/or etching depths occur. The issues are due to non-conventional plasma concentration from parts of the photoresist patterns 112a in the array region 102 being more concentrated than those in the periphery region 104. The issue is called loading effect, in which depths of the openings in the periphery region 104 is deeper than those in the array region 102. Further, when device density is higher, loading effect is more serious.